The invention relates to gate technology for strained surface channel and strained buried channel MOSFET devices.
The advent of high quality relaxed SiGe layers on Si has resulted in the demonstration of field effect transistors (FETs) with carrier channels enhanced via strain. The strain can be incorporated in the channel due to the lattice mismatch between the channel and the relaxed SiGe created by a change in the Ge concentration between the channel layer and the relaxed SiGe layer. For example, a Ge concentration of 20% Ge in the relaxed buffer is high enough such that a thin strained Si layer can exhibit electron mobilities as high as 1000-2900 cm2/V-sec. Also, if the Ge concentration in the channel is greater than the concentration in the buffer, hole channel mobilities can be enhanced. For example, a relaxed buffer concentration of 60-70% Ge can compressively strain a Ge channel layer, creating potentially extremely high hole mobilities.
Although the exact physics of carrier scattering are not known inside short-channel FETs, one thing is clear: these enhanced mobilities translate into increased device performance, even at very short gate lengths. In addition to higher speed and a different power-delay product, the use of strained channels allows for the incorporation of new FET structures into Si-based circuits. Thus, it is anticipated that the high performance, new flexibility in device design, and economics of using a Si-based platform will lead to a plethora of new circuits and products.
With regards to these new circuits and products, the devices based on metal-insulator-semiconductor (MIS) or metal-oxide-semiconductor (MOS) gate technology are the most intriguing, since these devices can follow very closely the processes already used in Si VLSI manufacturing. Two main types of devices are of particular interest: the surface channel device and the buried channel device, examples of which are shown in FIGS. 1A and 1B.
FIG. 1A is a cross section of a block diagram of a strained Si surface channel device 100, in which a thin strained Si layer 102 is grown atop a relaxed SiGe virtual substrate. The SiGe virtual substrate can be relaxed SiGe 104 on a SiGe graded buffer 105 (as shown in FIG. 1a), relaxed SiGe directly on a Si substrate 106, or relaxed SiGe on an insulator such as SiO2. The device also includes a SiO2 layer 108 and gate material 110.
FIG. 1B is a cross section of a block diagram of a strained Si buried channel device 112, in which a SiGe layer 116 and a second strained Si layer 120 (used for gate oxidation) cap the strained Si channel layer 114. The structure also includes a graded SiGe buffer layer 125 and a second relaxed SiGe layer 126. In both device configurations, a gate oxide 122 is grown or deposited and the gate material 124 is deposited to form the (MOS) structure. Although only devices with strained Si channels are shown in FIGS. 1A and 1B, the invention is applicable to any heterostructure device fabricated on a relaxed SiGe platform. For example, the heterostructure strained channel could be Ge or SiGe of a different Ge content from that of the underlying SiGe virtual substrate. However, the following description will focus on the applicability of the invention to the strained Si device variants illustrated in FIGS. 1A and 1B.
In order to form the MOS gate of the heterostructure device, the SiGe would ideally be oxidized directly in the buried channel device, and the strained Si would be oxidized directly in the surface channel device. Unfortunately, there are problems due to the nature of the Si/SiGe heterostructures in both cases that render the direct oxidation process unsatisfactory.
First consider the surface channel device. Since Si is being oxidized, the interface state density at the resulting SiO2/Si interface is low, and an electrically high quality interface results. However, all oxidation and cleaning processes during the device and circuit fabrication consume the Si material. In conventional Si processing, there is generally little worry about Si consumption since so little material is consumed compared to any limiting vertical dimension early in the fabrication process. However, in the case of the strained surface channel FET described here, the top strained Si layer is typically less than 300 xc3x85 thick, and thus too much Si consumption during cleaning and oxidation steps will eliminate the high mobility channel.
One obvious solution is to simply deposit extra Si at the surface, planning for the removal of the Si that occurs during processing. However, the channel strain, which gives the channel its higher carrier mobility, limits the Si layer thickness. At a great enough thickness, the Si layer will begin to relax, introducing misfit dislocations at the Si/SiGe interface. This process of dislocation introduction has two deleterious effects on device performance. First, the strain in the Si is partially or completely relieved, potentially decreasing the carrier mobility enhancements. Second, dislocations can scatter carriers, decreasing carrier mobility. Dislocations can also affect device yield, reliability, and performance.
The buried channel case appears to be a better situation at first, since the Si layer thickness is buried. However, in this case, direct oxidation of SiGe creates a very high interface state density at the oxide/SiGe interface, leading to poor device performance. A known solution in the field is to create a thin Si layer at the surface of the buried channel structure. In this structure, the surface layer is carefully oxidized to nearly consume the entire top Si layer. However, a thin layer of un-oxidized Si is left so that the interface to the oxide is the superior SiO2/Si interface rather than the problematic oxide/SiGe interface. Although this sacrificial surface Si layer solves the interface electronic property issue, the structure now has the same limits as the structure described above, i.e., the sacrificial Si layer will be slowly etched away during Si processing, possibly leading to exposure of the SiGe and degradation of the electrical properties of the interface as described.
In accordance with the invention there is provided a method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1xe2x88x92xGex layer on a substrate, a strained channel layer on the relaxed Si1xe2x88x92xGex layer, and a Si1xe2x88x92yGey layer; removing the Si1xe2x88x92yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.